1. Field of the Invention
The present invention relates to an electronic circuit in which a clock line for transmitting a clock signal is extended, and more particularly an electronic circuit having a logic circuit operative by a clock signal in a macro and a block of a semiconductor integrated circuit of an LSI.
2. Description of the Related Art
Recently, as a semiconductor integrated circuit is integrated with a high density, a logic circuit is more complicated while a macro-processing technology is developed. This brings about many factors which affect to be disadvantageous in production of an integrated circuit for a stable operation. Particularly, as an increment of data sizes to be dealt with inside an LSI and a complication of commands are advanced, it begins that a long parallel wiring cannot be ignored by an influence of an increment of the number of bits in a macro and a block. According to the prior art, a high-integration is advanced by means of rationalization of logic circuits and efficient use of wiring. The high-integration is associated with a big problem also when a shield of noises emanating from a clock signal line is ensured. It is possible to suppress noises in such a way that a wiring of a shield wire is performed along the clock signal line. However, an insertion of the shield wire serves to degrade an integration degree of IC. With respect to a technology in which a degradation of the integration degree of IC is prevented, and a shield is performed, Japanese Patent Laid Open Gazette Hei.10-242282 discloses a technology that in a mode wherein a clock line to be shield is activated, a scan clock signal line on which a signal transmission is not performed is wired along the clock signal line to be shield, so that the scan clock signal line is used also as a shield wire.
As mentioned above, today, as high-integration complication of a circuit is further advanced, a bit length of data is elongated, such a long parallel wiring that a cross talk is generated in the block cannot be ignored on a design basis. Only such a concept that the scan clock signal line is wired along the clock signal line, as disclosed in the above-mentioned Japanese Patent Laid Open Gazette Hei.10-242282, is insufficient at the design stage for excluding the cross talk due to such a long wiring in block. Thus, it is considered that there is a need to improve the technology as mentioned above. There is considered, for example, a scan system and a reset system, a case where even if a certain length of wiring may be driven for a signal which is accepted in a slow cycle, a pulse width is increased while a miniaturization of an LSI circuit is advanced, so that a clock, which is short in a cycle and strong in a driving force, is used. In this case, while a propagation speed of the signal is ensured, it may happen that elongation of the wiring brings about such a situation that even if it is intended to hold the scan clock signal line at a predetermined position for a shield by the conventional scan system of drive, it is insufficient to shield a clock noise emanated from the clock signal line, which is strong in a shield phenomenon.